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| 1 250mhz triple differential receiver/ equalizer with i 2 c interface isl59911 the isl59911 is a triple channel differential receiver and equalizer optimized for rgb and ypbpr video signals. it contains three high speed differential receivers with programmable frequency co mpensation. the isl59911 features manual or automatic offset calibration and 4db of gain adjustment range with a resolution of 0.1db. the isl59911 has a bandwidth of 250mhz and consumes only 110ma from a 5v supply in normal operation. when deasserted, the enable pi n puts the amplifiers into a low power, high impedance stat e, minimizing power when not needed and also allowing multiple devices to be connected in parallel, allowing two or more isl59911 devices to function as a multiplexer. the isl59911 can also directly decode the sync signals encoded onto the common modes of three pairs of cat 5 cable (by an isl59311, el4543, or sim ilar device) or it can output the actual common mode voltages for each of the three channels. the isl59911 is available in a 32 ld qfn package and is specified for operation over the full -40c to +85c temperature range. features ? 250mhz -3db bandwidth ? 5 adjustable eq bands: 100mhz, 20mhz, 6mhz, 1mhz, and 200khz ? 3rd-order lowpass filter at output with programmable corner ? 4db fine gain control wi th 0.1db (7-bit) resolution ? offset calibration minimizes output offset voltage ? decodes h sync and v sync signals embedded in common mode ?i 2 c interface with four unique addresses ? 5v supplies @ 110ma ? 32 ld 5mm x 6mm qfn package applications ? kvm monitor extension ? digital signage ? general-purpose twisted-pair receiving and equalization ? high-resolution security video twisted-pair rgb video receiver 74hc04 or similar termination network r in - r in + isl59911 50 50 50 1k 0.1f g in + g in - b in + b in - scl sda system micro- controller i 2 c interface isl59311 or el4543 triple differential video driver r p r p addr0 addr1 r out g out b out hs out /r cm vs out /g cm b cm nc r ref g ref b ref termination network termination network up to 300m of cat x cable +5v enable -5v +5v c bypass * x3 c bypass * x3 v+ v- and thermal pad gnd +5v 75 x3 isl59920 isl59921 isl59922 or isl59923 video delay line figure 1. typical application circuit *see ?power supply bypassing? on page 10 for more information. caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. september 2, 2011 fn7548.0
isl59911 2 fn7548.0 september 2, 2011 block diagram pin configuration isl59911 (32 ld qfn) top view sync decoding differential to single- ended conversion + common mode extraction 100mhz 20mhz 6mhz 1mhz i 2 c interface noise filter r in + cm g r out b out g out cm r cm b hs out /r cm vs out /g cm b cm r in - g in + g in - b in + b in - scl sda control logic enable 1 2 3 200khz addr0 addr1 equalizer r ref b ref g ref gain (r) gain (g) gain (b) 9 thermal pad 25 24 23 22 21 20 19 32 31 30 29 28 1 2 3 4 5 6 7 addr1 v- d v- v+ r r out v- r v- g g out v+ g addr0 sda scl gnd 8 18 26 v+ b r in + r in - g in + 10 11 12 13 14 v+ hs out /r cm vs out /g cm b cm enable 17 16 b out 27 15 b ref g in - b in + b in - gnd v- b gnd exposed dieplate should be connected to v- (-5v) g ref r ref ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # isl59911irz 59911 irz 32 ld qfn l32.5x6c ISL59911IRZ-EVALZ evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding comp ounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-fr ee products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl59911 . for more information on msl please see techbrief tb363 . isl59911 3 fn7548.0 september 2, 2011 pin descriptions pin number pin name pin function 1 addr1 digital input. i 2 c address select bit 1, used with addr0 to select the isl59911 i 2 c address (see ?isl59911 serial communication? on page 13). note: if power supply sequencing cannot be guaranteed, addr1 must be held low during power-up. see ?power supply sequencing? on page 10 for more information. 2v- d power supply pin. -5v for internal digital logi c (internal logic operates between gnd and v- d ). connect to the same -5v supply as v-. 3 v- power supply pin. -5v supply for analog core of chip , also tied to thermal pad. connect to a -5v supply. 4r in + analog input. red positive differential input 5r in - analog input. red negative differential input 6g in + analog input. green positive differential input 7g in - analog input. green negative differential input 8b in + analog input. blue positive differential input 9b in - analog input. blue negative differential input 10 v+ power supply pin. +5v supply for analog core of chip. connect to a +5v supply. 11 hs out /r cm output configuration (note 4) = 0: digital output. decode d horizontal sync signal output configuration (note 4) = 1: analog output. red common-mode voltage at inputs 12 vs out /g cm output configuration (note 4) = 0: digital output. decoded vertical sync signal output configuration (note 4) = 1: analog output. green common-mode voltage at inputs 13 b cm output configuration (note 4) = 0: digital output. logic low output configuration (note 4) = 1: analog output. blue common-mode voltage at inputs 14 enable digital input. chip enable logic signal. 0v: all analog circuitry turned off to reduce current. 5v: normal operation. 15 gnd power supply pin. ground reference for isl59911. this pin must be tied to gnd. 16 b ref analog input. blue channel analog offset reference voltage. typically tied to gnd. 17 v- b power supply pin. -5v supply for blue output buffer. connect to the same -5v supply as v-. 18 b out analog output. blue output voltage referenced to b ref pin. 19 v+ b power supply pin. +5v supply for blue output buffer. connect to the same +5v supply as v+. 20 v+ g power supply pin. +5v supply for green output buffer. connect to the same +5v supply as v+. 21 g out analog output. green output voltage referenced to g ref pin. 22 v- g power supply pin. -5v supply for green output buffer. connect to the same -5v supply as v-. 23 v- r power supply pin. -5v supply for red output buffer. connect to the same -5v supply as v-. 24 r out analog output. red output voltage referenced to r ref pin. 25 v+ r power supply pin. +5v supply for red output buffer. connect to the same +5v supply as v+. 26 gnd power supply pin. ground reference for isl59911. 27 g ref analog input. green channel analog offset reference voltage. typically tied to gnd. 28 r ref analog input. red channel analog offset reference voltage. typically tied to gnd. 29 gnd power supply pin. ground reference for isl59911. this pin must be tied to gnd. 30 scl digital input. i 2 c clock input 31 sda digital input/open-drain digital output. i 2 c data input/output 32 addr0 digital input. i 2 c address select bit 0, used with addr1 to select the isl59911 i 2 c address. thermal pad thermal pad power supply pin. connect to -5v supply plan e with multiple vias to reduce thermal resistance and more effectively spread heat from the isl59911 to the pcb. note: 4. output configuration is controlled via configuration register 0x01, bit 0. isl59911 4 fn7548.0 september 2, 2011 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = +25c) thermal information v+ = v+ r = v+ g = v+ b , v- = v- r = v- g = v- b = v- d supply voltage between v+ and v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v maximum absolute slew rate of v+ and v- . . . . . . . . . . . . . . . . . . . 1v/s maximum continuous output current per channel . . . . . . . . . . . . . 30ma power dissipation. . . . . . . . . . . . . . . . see ?power dissipation? on page 12 pin voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- - 0.5v to v+ + 0.5v esd ratings human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . 7000v machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 300v charged device model (tested per jesd22c101c) . . . . . . . . . . . . 2000v latch up (tested per jesd78; class ii, level a) . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 32 ld qfn (notes 5, 6) . . . . . . . . . . . . . . . . 31 2.1 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c die junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c v+ supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v v- supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.5v to -5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v+ = v+ r = v+ g = v+ b = +5v, v- = v- r = v- g = v- b = v- d = -5v, t a = +25c, all registers at default settings (equalizer stages set to minimum boost, noise fi lter set to max bandwidth, x2 gain mode, gain dc = 0db), all analog inputs at 0v, auto offset calibration executed, r l = 5pf || (75 + 75 ) to gnd, thermal pad connected to -5v, unless otherwise specified. parameter description conditions min (note 7) typ max (note 7) unit power supply positive supply voltage (v+) v+ = v+ r = v+ g = v+ b 4.5 5.5 v negative supply voltage (v-) v- = v- r = v- g = v- b = v- d -4.5 -5.5 v operating current (i d +) sum of currents into all v+ pins 110 140 ma operating current (i d -) sum of currents out of all v- pins, including thermal pad 105 130 ma disabled current (i d + disabled ) sum of currents into all v+ pins enable = 0v 2.5 3.5 ma disabled current (i d - disabled ) sum of currents into all v- pins, including thermal pad enable = 0v 0.35 2.5 ma psrr dc power supply rejection ratio 55 db ac performance bw full power bandwidth 250 mhz gain 100mhz maximum boost @ 100mhz all three 100mhz filters set to maximum 26 db gain 20mhz maximum boost @ 20mhz 20mhz filter set to maximum 9.5 db gain 6mhz maximum boost @ 6mhz 6mhz filter set to maximum 7.5 db gain 1mhz maximum boost @ 1mhz 1mhz filter set to maximum 3.1 db gain 0.2mhz maximum boost @ 200khz 200khz filter set to maximum 0.75 db gain dc dc gain adjustment range 4 db f noise_min -3db corner freq of noise filter, high noise filter register = 0x0 250 mhz f noise_max -3db corner freq of noise filter, low noise filter register = 0xf 50 mhz sr diff output slew rate v in = -1v to +1v 1 v/ns thd total harmonic distortion f = 10mhz, 0.7v p-p input sine wave -45 -60 dbc isl59911 5 fn7548.0 september 2, 2011 bw cm common mode amplifier bandwi dth 10k || 5pf load 24 mhz sr cm common mode slew rate v in = -0.5v to +1.5v 0.1 v/ns input characteristics cmir common-mode input range different ial signal passed undistorted. effective headroom is reduced by the p-p amplitude of differential swing divided by 2. -3.2/+4.0 v cmrr common-mode rejection ratio measured at 100khz 88 db measured at 10mhz 58 db c indiff differential input capacitance capacitance between v inp and v inm 0.5 pf r indiff differential input resistance resistance between v in + and v in - (due to common mode input resistance) 20 k c incm cm input capacitance capacitance from v in + and v in - to gnd 1.3 pf r incm cm input resistance resistance from v in + and v in - to gnd 25 k v indiff_p-p max p-p differential input range delta v in + - v in - when slope gain falls to 0.9 1.9 v output characteristics v out output voltage swing 2.75 v i out output drive current r l = 10 , v in + - v in - = 2v 22 ma v(v out ) os output offset voltage post-offset calibration -20 -8 +5 mv r(v cm ) cm output resistance of vcm_r/g/b (cm output mode) at 100khz 2.5 gain gain x1 mode x2 mode 0.95 1.9 1.0 2.0 1.05 2.1 v/v gain channel-to-channel gain mismatch x1 and x2 modes 3 % o noise integrated noise at output inputs @ gnd through 50 . 0m of equalization (nominal) 300m of equalization 4 20 mv rms syncout hi high level output on vs/hs out 10k || 5pf load, sync output mode v+ - 1.5 v syncout lo low level output on vs/hs out 10k || 5pf load, sync output mode 0.4 v scl, sda pins f max maximum i 2 c operating frequency 400 khz v ol sda output low level v sink = 6ma 0.4 v v ih input high level 3v v il input low level 1.5 v v hyst input hysteresis 0.55 v i leakage input leakage current 1 a t glitch maximum width of glitch on scl (or sda) guaranteed to be rejected 50 ns enable, addr0, addr1 pins v ih input high level 3v v il input low level 0.8 v i leakage input leakage current 1 a note: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications v+ = v+ r = v+ g = v+ b = +5v, v- = v- r = v- g = v- b = v- d = -5v, t a = +25c, all registers at default settings (equalizer stages set to minimum boost, noise fi lter set to max bandwidth, x2 gain mode, gain dc = 0db), all analog inputs at 0v, auto offset calibration executed, r l = 5pf || (75 + 75 ) to gnd, thermal pad connected to -5v, unless otherwise specified. (continued) parameter description conditions min (note 7) typ max (note 7) unit isl59911 6 fn7548.0 september 2, 2011 typical performance curves figure 2. nominal frequency response with default settings figure 3. frequency response vs 100mhz bits 1:0 figure 4. frequency response vs 100mhz bits 4:2 figure 5. frequency response vs 100mhz bits 7:5 figure 6. frequency response vs 20mhz bits 7:4 figure 7. frequency response vs 6mhz bits 3:0 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 0.1 1 10 100 1000 frequency (mhz) magnitude (db) x2 x1 -2 0 2 4 6 8 10 12 0.01 0.1 1 10 100 1000 frequency (mhz) magnitude (db) code 3 code 2 code 1 code 0 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.01 0.1 1 10 100 1000 frequency (mhz) magnitude (db) code 0 code 1 code 2 code 4 code 3 code 5 code 6 code 7 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.01 0.1 1 10 100 1000 frequency (mhz) magnitude (db) code 0 code 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0.1 1 10 100 1000 frequency (mhz) magnitude (db) code 00 code 0f -1 0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1 10 100 1000 frequency (mhz) magnitude (db) code 0f code 00 isl59911 7 fn7548.0 september 2, 2011 figure 8. frequency response vs 1mhz bits 7:4 f igure 9. frequency response vs 200khz bits 3:0 figure 10. frequency response vs low pass filter bits 3:0 typical performance curves (continued) -1 0 1 2 3 4 5 6 0.01 0.1 1 10 100 1000 frequency (mhz) magnitude (db) code 0f code 00 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0.01 0.1 1 10 100 1000 frequency (mhz) magnitude (db) code 0f code 00 -60 -50 -40 -30 -20 -10 0 10 10 100 1000 frequency (mhz) magnitude (db) code 00 code 01 code 09 code 0a code 0b code 0f isl59911 8 fn7548.0 september 2, 2011 register listing address register (default value) bit(s) function name description 0x00 device id (read only) 3:0 device revision 0 = initial silicon, 1 = first revision, etc. 7:4 device id 0x10 = isl59911 0x01 general configuration (0x02) 0 output configuration 0: h sync + v sync (like el9111 and isl59910) 1: v cm (like el9112 and isl59913) 1 nominal gain 0: 0db (1v/v) 1: 6db (2v/v) 2 power down 0: normal operation 1: low power mode, all amplifiers turned off 0x02 high adjust (0x00) 1:0 1 00mhz stage 1 00b: min boost 11b: max boost 4:2 100mhz stage 2 000b: min boost 111b: max boost 7:5 100mhz stage 3 000b: min boost 111b: max boost 0x03 mid adjust (0x00) 3:0 6mhz 0000b: min boost 1111b: max boost 7:4 20mhz 0000b: min boost 1111b: max boost 0x04 low adjust (0x00) 3:0 200khz 0000b: min boost 1111b: max boost 7:4 1mhz 0000b: min boost 1111b: max boost 0x05 noise filter adjust (0x00) 3:0 noise filter ad justs -3db frequency of noise filter at output 0x0: max frequency 0xf: min frequency 0x06 red channel gain (0x40) 6:0 red gain 0x00: -6db 0x40: 0db 0x7f: +6db note: due to gain trim at production test, the minimum guaranteed usable gain range is 4db. 0x07 green channel gain (0x40) 6:0 green gain 0x00: -6db 0x40: 0db 0x7f: +6db note: due to gain trim at production test, the minimum guaranteed usable gain range is 4db. 0x08 blue channel gain (0x40) 6:0 blue gain 0x00: -6db 0x40: 0db 0x7f: +6db note: due to gain trim at production test, the minimum guaranteed usable gain range is 4db. 0x09 red channel manual offset (0x00) (default is auto-calibrated) 6:0 red offset 0x00: -400mv offset 0x7f: +400mv offset (output referred) 7 manual offset control (red) 0: offset is auto calibrated - value in bits 6:0 is ignored 1: offset dac set to value in bits 6:0 0x0a green channel manual offset (0x00) (default is auto-calibrated) 6:0 green offset 0x00: -400mv offset 0x7f: +400mv offset (output referred) 7 manual offset control (green) 0: offset is auto calibrated - value in bits 6:0 is ignored 1: offset dac set to value in bits 6:0 isl59911 9 fn7548.0 september 2, 2011 0x0b blue channel manual offset (0x00) (default is auto-calibrated) 6:0 blue offset 0x00: -400mv offset 0x7f: +400mv offset (output referred) 7 manual offset control (blue) 0: offset is auto calibrated - value in bits 6:0 is ignored 1: offset dac set to value in bits 6:0 0x0c offset calibration control (0x00) 0 start cal set to 1 to initiate offset calibration. bit is reset to 0 when calibration is complete (in ~3s or less). 1 cal mode 0: analog inputs disconnected from external pins and internally shorted together during calibration. 1: analog inputs remain conn ected to external circuitry during calibration. useful for calibrating out system-wide offsets. external offsets of up to ~160mv can be eliminated. 2 short inputs 0: normal operation 1: inputs shorted together (independent of the cal mode bit) 0x0d - 0x12 reserved 7:0 reserved reserved. do not write anything to these addresses. 0x13 initialization 7:0 initialization after init ial power on, write 0x06 to this register, followed by a write of 0x00 to this register. note: all registers are read/write unless otherwise noted . register listing (continued) address register (default value) bit(s) function name description isl59911 10 fn7548.0 september 2, 2011 applications information isl59911 overview differential video signals sent over long distances of twisted pair wire encounter are increasingly attenuated as frequency and distance increase, resulting in loss of high frequency detail (blurring). the exact loss characteristic is a function of the wire gauge, whether the pairs are shielded or unshielded, the dielectric of the insulation, and the length of the wire. the loss mechanism is primarily skin effect. the signal can be restored by applying a filter with the inverse transfer function of the cable to the far end signal. the isl59911 is designed to compensate for losses due to long cables, and incorporates the functionality an d flexibility to match a wide variety of loss characteristics. power supply sequencing power to the isl59911?s negative supply pins should be applied before the positive supply ramps. as shown in figure 11, v- should reach -3v be fore v+ reaches 1v. if this power supply sequence cannot be guaranteed, then the addr1 pin must be held low during power-up until v- has crossed -3v. if this power supply sequencing requirement is not met and if addr1 is high, there is a small chance that the isl59911 factory trim will become permanently corrupted. power supply bypassing for best performance, all ics need bypass capacitors across some or all of their power supply pins. the best high-frequency decoupling is achieved with a 0.1 f capacitor between each power supply pin and gnd. adjace nt supply pins (pins 2 and 3, 19 and 20, 22 and 23, and 25 and 26) can share the same decoupling capacitor. keep the path to both pins as short as possible to minimize inductance and resistance. pins 3 and 10 provide power to the internal equalizer, while supply pins between pin 17 and pin 25 provide power to the analog output buffers. for best performance, the equalizer supplies should be somewhat isolated from the buff er supplies. a separate path back to the power source should be adequate. a 10 f capacitor on each of the v+ and v- supplies provides sufficient low-frequency decoupling. the 10 f capacitors do not need to be particularly close to the isl59911 to be effective, but should still have a low-impedance path to the supply rails. in many mixed-signal ics, separation of the analog and digital supplies and grounds is critical to prevent digital noise from appearing on the analog signals. because the digital logic in the isl59911 is only active during a one-time configuration, the analog and digital supply pins (and grounds) can be connected together, simplifying pcb layout and routing. input termination the differential input signal fr om a cat x cable should have a characteristic impedance of 100 and is therefore terminated by the two 50 resistors across the differential inputs, as shown in figure 1 on page 1. the 50 resistor and 0.1f capacitor connected to the midpoint keep the ac impedance low at high frequencies, providing common-mode ac termination while allowing the low-frequency component of the common mode (containing the embedded h and v sync signals) to move freely. the 1k resistor provides a higher-impedance dc path to ground, so the common mode voltage is set to 0v when no cable is connected. device initialization to ensure that the isl59911 fu nctions properly, the following steps must be taken after initial power-up: 1. ensure that the enable pin is high. 2. through the serial interface, write 0x06 to register 0x13, then write 0x00 to the same register. this ensures that the dc gain of the device is accurate. 3. perform an offset calibration by setting bit 0 of register 0x0c to 1. the bit is automatically resets to 0 upon completion of calibration. if offset calibra tion is not performed, the isl59911 may have large dc offsets. communicating with the isl59911 the isl59911 is controlled through the industry standard i 2 c serial interface. adjustments to the frequency response over five distinct frequency bands, gain and offset fine-tuning, and several other functions are made through this interface as described in the register listing starting on page 8. this level of control enables much more accurate an d flexible response matching than previous solutions. the isl59911 also has an external chip enable (enable) pin, allowing hardware control of whether the chip is operating or in a low-power standby mode. programming the isl599 11 for a specific cable and length determining the optimum settings for the isl59911?s multiple equalizer frequencies, gain, and low pass filter can initially seem quite challenging. to equalize any cable type of any length, transmit a step (a pure white sc reen works well, since the video in h sync region is black) and adjust the filters, starting at 200khz and working up to 100mhz, so that the response at the receive end is as flat as possible. once the response is flat, the gain should be adjusted as necessary to compensate for the dc losses. this technique is not usually practical in the field, where the best solution is a lookup table for ea ch cable type. table 1 shows the best values for a typical cat 5 cable. +1v figure 11. power supply sequencing -3v t > 0ms v+ v- isl59911 11 fn7548.0 september 2, 2011 offset calibration historically, programmable video equalizer ics have had large and varying offset voltages, often requiring external circuitry and/or manual trim to reduce the offset to acceptable levels. the isl59911 improves upon this by adding an offset calibration circuit that, when triggered by setting bit 0 of i 2 c register 0x0c, shorts the inputs together internally, compares the r out , g out , and b out voltages to their corresponding r ref , g ref , and b ref voltages and uses a dac with a successive-approximation technique to minimize the delt a between them (see figure 12). when the isl59911 is first powered up, the offset error is undefined until an offset calibration is performed. the output offset voltage of the isl59911 also varies as the filter and gain settings are adjusted. to minimize offset, always perform an offset calibration after finalizing the filter and gain settings. an offset calibration only takes about 3 s, so offset calibrations can be performed after every register write without adding significant time to the adjustment process. this minimizes offset throughout the entire equali zation adjustment procedure. output signals the r out , g out , and b out outputs can drive either a standard 75 video load in x1 gain mode or a 150 source-terminated load (75 in series at source end [isl59911 output pin], plus 75 termination to ground at receive end) in x2 mode. if the output of the isl59911 is goin g directly into an isl59920 or similar delay line, termination to ground is not necessary, however, a ~75 series resistor at each output pin will help isolate the outputs from the pcb trace capacitance, improving the flatness of the frequency response. when enable is low, the r out , g out , and b out outputs are put in a high-impedance state, allo wing multiple isl59911 devices to be configured as a multiplexer by paralleling their outputs and using enable to select the active rgb channel. common mode and h sync /v sync outputs in addition to the incoming di fferential video signals, the isl59911 also processes the common mode voltage on the differential inputs and can output the signal in one of two ways (as determined by the output configuration bit in register 0x01). when the output configuration bit is set to 0 (the default), the common mode input voltages ar e sent to comparators that decode the voltage into h sync and v sync signals according to the el4543/isl59311 standard encoding scheme shown in figure 13 and in table 2 on page 11. the h sync signal appears on the hs out /r cm pin, the v sync signal on vs out /g cm . the b cm output pin is held at a logic low (0v). to minimize noise coupling into the analog sectio n from the sync output drivers, the hs out and vs out outputs have limited current drive, and should be buffered by 74hc04 or similar cmos buffers, as shown in figure 1, before driving any significant loads (such as a vga cable). when the output configuration bit is set to 1, buffered versions of the three common mode input voltages are available on the r cm , g cm , and b cm pins. making the raw common mode signal available allows for custom encoding schemes and/or transmission of analog signals on the video signals? common mode. table 1. cat 5 look-up table length (m) reg 2 reg 3 reg 4 reg 5 reg 6-8 0 0x00 0x00 0x00 0x00 0x40 25 0x20 0x11 0x10 0x00 0x40 50 0x24 0x22 0x21 0x01 0x44 75 0x25 0x33 0x31 0x01 0x44 100 0x49 0x44 0x42 0x01 0x48 125 0x69 0x55 0x53 0x02 0x48 150 0x89 0x75 0x62 0x02 0x4c 175 0x92 0x86 0x72 0x04 0x4c 200 0x96 0x96 0x82 0x06 0x50 225 0x97 0xa7 0x93 0x08 0x50 250 0xb7 0xb8 0xb2 0x09 0x54 275 0xd7 0xc9 0xc3 0x0a 0x54 300 0xf7 0xea 0xd2 0x0c 0x58 v out v ref v in + v in - eq and gain dac sar logic output buffer comparator input buffer figure 12. offset calibration (one channel shown) table 2. h and v sync decoding red cm green cm blue cm h sync v sync 2.5v 3.0v 2.0v low low 3.0v 2.0v 2.5v low high 2.0v 3.0v 2.5v high low 2.5v 2.0v 3.0v high high time (0.5ms/div) blue cm green cm red cm v sync h sync 0v 2.5v 0v 2.5v 2.0v 3.0v 2.0v 3.0v 2.0v 3.0v figure 13. h and v sync signal encoding isl59911 12 fn7548.0 september 2, 2011 power dissipation the isl59911 is designed to operate with 5v supply voltages. the supply currents are tested in production and guaranteed to be less than 140ma per channel. operating at 5v power supply, the total power dissipation is shown by equation 1: where: ?pd max = maximum power dissipation ?v s = supply voltage = 5v ?i max = maximum quiescent supply current = 140ma ?v outmax = maximum output voltage swing of the application = 2v ? the 3 term comes from the number of channels ?r l = load resistance = 150 ?pd max = 1.4w ja required for long term reliable operation can be calculated. this is done using equation 2: where: t j is the maximum juncti on temperature (+150c) t a is the maximum ambient temperature (+85c) for a 32 ld qfn package in a proper layout pcb heatsinking copper area, 31c/w ja thermal resistance can be achieved. to disperse the heat, the bottom heat spreader must be soldered to the pcb. heat flows through the heatspreader to the circuit board copper, then spreads and converts to air. thus the pcb copper plane becomes the heatsink. this has proven to be a very effective technique. a separate application note that details the 32 pin qfn pcb design cons iderations is available. pd max 2v s i smax 3v s ( - v outmax ) v outmax r l ------------------------ + = (eq. 1) ja t j t a ? () pd ? 46 c () w ? = = (eq. 2) isl59911 13 fn7548.0 september 2, 2011 isl59911 serial communication overview the isl59911 uses the i 2 c serial bus protocol for communication with its host (mas ter). scl is the serial clock line, driven by the host, and sda is the serial data line, which can be driven by all devices on the bus. sda is open drain to allow multiple devices to share th e same bus simultaneously. communication is accomplished in three steps: 1. the host selects the isl5991 1 it wishes to communicate with. 2. the host writes the initial isl59911 configurat ion register address it wishes to write to or read from. 3. the host writes to or reads from the isl59911s configuration register. the isl59911s internal address pointer auto increments, so to read registers 0x00 through 0x1b, for example, one would write 0x00 in step 2, then repeat step three 28 times, with each read returning the next register value. the isl59911 has a 7-bit address on the serial bus, 10001 isl59911 14 fn7548.0 september 2, 2011 configuration register write figure 17 shows two views of the steps necessary to write one or more words to the configuration register. scl sda data stable data change data stable figure 16. valid data changes on the sda bus d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 isl59911 register data write(s) this is the data to be written to the isl59911?s configuration register. note: the isl59911 configuration register?s address pointer auto-increments after each data write. repeat this step to write multiple sequential bytes of data to the configuration register. a6 a5 0 r/w isl59911 register address write this is the address of the isl59911?s configuration register that the following byte will be written to. isl59911 serial bus figure 17. configuration register write start command stop command (repeat if desired) signals the beginning of serial i/o signals the ending of serial i/o s t a r t s t o p data write* register address serial bus address a c k aaaaaaaa a c k dddddddd a c k aaaaaaa0 * the data write step can be repeated to write to the isl59911?s configuration register sequentially, beginning at the register address written in the previous step. sda bus signals from the isl59911 signals from the host isl59911 device select address write the first 7 bits of the first byte select the isl59911 on the 2-wire bus at the address set by the addr0 and addr1 pins. the r/w bit is a 0, indicating that the next transaction will be a write. addr1 addr0 01 00 1 isl59911 15 fn7548.0 september 2, 2011 configuration register read figure 18 shows two views of the steps necessary to read one or more words from the configuration register. figure 18. configuration register read a0 a7 a2 a4 a3 a1 a6 a5 r/w isl59911 register address write this sets the initial address of the isl59911?s configuration register for subsequent reading. isl59911 serial bus start command signals the beginning of serial i/o isl59911 serial bus address write this is the same 7-bit address that was sent previously, however the r/w bit is now a 1, indicating that the next transaction(s) will be a read. d7 d6 d5 d2 d4 d3 d1 d0 isl59911 register data read(s) this is the data read from the isl59911?s configuration register. note: the isl59911 configuration register address pointer auto-increments after each data read: repeat this step to read multiple sequential bytes of data from the configuration register. r/w isl59911 serial bus start command stop command (repeat if desired) ends the previous transaction and starts a new one. signals the ending of serial i/o s t a r t s t o p data read* sda bus signals from the isl59911 signals from the host register address serial bus address a c k aaaaaaaa a c k dddddddd a c k aaaaaaa0 * the data read step may be repeated to read from the isl59911?s configuration register sequentially, beginning at the register address written in the previous two steps. r e s t a r t serial bus address a c k aaaaaaa1 isl59911 device select address write the first 7 bits of the first byte select the isl59911 on the 2-wire bus at the address set by the addr0 and addr1 pins. r/w = 0, indicating that the next transaction will be a write. 0 addr1 addr0 01 00 1 1 addr1 addr0 01 00 1 isl59911 16 fn7548.0 september 2, 2011 products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl59911 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 9/2/11 fn7548.0 initial release. isl59911 17 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7548.0 september 2, 2011 for additional products, see www.intersil.com/product_tree quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) pin #1 i.d. mark 2 1 3 (n-2) (n-1) n (n/2) 2x 0.075 top view (n/2) ne 2 3 1 pin #1 i.d. (n-2) (n-1) n b l n leads bottom view detail x plane seating n leads c see detail "x" a1 (l) n leads & exposed pad 0.10 side view 0.10 b a m c c b a e 2x 0.075 c d 3 5 7 (e2) (d2) e 0.08 c c (c) a 2 c l32.5x6c (one of 10 packages in mdp0046) 32 lead quad flat no-lead plastic package (compliant to jedec mo-220) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 0.00 0.02 0.05 - d 5.00 bsc - d2 3.50 ref - e 6.00 bsc - e2 4.50 ref - l 0.35 0.40 0.45 - b 0.23 0.25 0.27 - c 0.20 ref - e 0.50 bsc - n 32 ref 4 nd 7 ref 6 ne 9 ref 5 rev 0 9/05 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminals on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be s quare or circular in shape with radius (b/2) as shown. |
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